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| White Electronic Designs WV3HG264M72EER-PD4 ADVANCED* 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, SO-DIMM, w/PLL FEATURES Registered 200-pin (SO-DIMM), Small-Outline dual in-line memory module Support ECC detection and correction Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 VCC = VCCQ = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Multiple internal device banks for concurrent operation Differential clock inputs (CK, CK#) Programmable CAS# latency (CL): 3, 4, 5*, and 6* Posted CAS# additive latency: 0, 1, 2, 3 and 4 On-die termination (ODT) 7.8s average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Utilizes 512Mb DDR2 SDRAM components Auto & self refresh (64ms: 8,192 cycle refresh) Gold edge contacts Dual Rank RoHS compliant JEDEC proposed Pin-out Package * 200 Pin SO-DIMM: 30.00mm (1.181") TYP. DESCRIPTION The WV3HG264M72EER is a 2x64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 64Mx8 bit DDR2 Synchronous DRAMs in FBGA packages, mounted on a 200-pin SODIMM FR4 substrate. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option OPERATING FREQUENCIES PC2-3200 Clock Speed CL-tRCD-tRP * Consult factory for availability PC2-4200 266MHz 4-4-4 PC2-5300* 333MHz 5-5-5 PC2-6400* 400MHz 6-6-6 200MHz 3-3-3 April 2006 Rev. 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VSS DQ0 DQ4 VSS DQ5 DQ1 VSS DQS0# DM0 DQS0 VSS VSS DQ6 DQ2 DQ7 DQ3 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DM1 DQS1# VSS DQS1 DQ14 VSS DQ15 DQ10 VSS DQ11 DQ20 VSS DQ21 DQ16 VSS DQ17 RESET# VSS DM2 DQS2# VSS DQS2 DQ22 VSS DQ23 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol DQ18 VSS DQ19 DQ28 VSS DQ29 DQ24 VSS DQ25 DM3 VSS VSS DQS3# DQ30 DQS3 DQ31 VSS VSS DQ26 CB4 DQ27 CB5 VSS VSS CB0 DM8 CB1 VSS VSS CB6 DQS8# CB7 DQS8 VSS VSS CB2 CKE0 CB3 CKE1 VSS NC NC VCC NC A12 A11 A9 VCC A7 A8 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol VCC A6 A5 A4 A3 VCC A2 A1 VCC A0 A10/AP BA1 BA0 VCC RAS# WE# VCC CS0# CAS# ODT0 CS1# A13 VCC VCC ODT1 CK NC CK# DQ32 VSS VSS DQ36 DQ33 DQ37 DQS4# VSS DQS4 DM4 VSS VSS DQ34 DQ38 DQ35 DQ39 VSS VSS DQ40 DQ44 DQ41 DQ45 Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol VSS VSS DQS5# DM5 DQS5 VSS VSS DQ46 DQ42 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6# VSS DQS6 DQ54 VSS DQ55 DQ50 VSS DQ51 DQ60 VSS DQ61 DQ56 VSS DQ57 DM7 VSS DQ62 DQS7# VSS DQS7 DQ63 DQ58 SDA VSS SCL DQ59 SA1 VCCSPD SA0 WV3HG264M72EER-PD4 ADVANCED PIN NAMES Pin Name A0-A13 BA0, BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0, ODT1 CK,CK# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# RESET# VCC VSS SA0-SA1 SDA VREF DM0-DM8 VCCSPD SCL NC Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock inputs Clock enable input Chip select input Row Address Strobe Column Address Strobe Write Enable Register reset input Core Power Ground SPD address Serial Data Input/Output Input/Output Reference Voltage Data-in mask Serial EEPROM power supply SPD Clock Input No connect April 2006 Rev. 2 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-PD4 ADVANCED FUNCTIONAL BLOCK DIAGRAM RCS1# RCS0# DQS0 DQS0# DM0 DM/ RDQS CS# DQS DQS# DQS4 DQS4# DM4 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5# DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6# DM6 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7# DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8# DM8 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Serial PD DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# SCL WP A0 A1 A2 SA2 SDA CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SA0 SA1 VCCSPD CS0# CS1# BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# PCK** PCK#** RESET#** Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 REGISTER X 2 1:2 R E G I S T E R RST# RCS0# CS# : DDR2 SDRAMs RCS1# CS# : DDR2 SDRAMs RBA0 - RBA1 BA0-BA1 : DDR2 SDRAMs RA0 - RA13 A0-A13 : DDR2 SDRAMs RRAS# RAS# : DDR2 SDRAMs RCAS# CAS# : DDR2 SDRAMs RWE# WE# : DDR2 SDRAMs RCKE0 CKE : DDR2 SDRAMs RCKE1 CKE : DDR2 SDRAMs RODT0 ODT : DDR2 SDRAMs RODT1 ODT : DDR2 SDRAMs VCC/VCCQ VREF VSS 120 CK CK# PLL CK CK# ** RESET#, PCK and PCK# connect to both Registers. Other signals connect to one of two Registers. Note: All resistor values are 22 ohms 5% unless otherwise specified. April 2006 Rev. 2 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-PD4 ADVANCED ABSOLUTE MAXIMUM RATINGS Symbol VCC VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Command/Address, RAS#, CAS#, WE#, CK, CK# DM IOZ IVREF Output leakage current; 0V Input leakage current; Any input 0V All voltages referenced to VSS Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage SPD Supply Voltage Symbol VCC VREF VTT VCCSPD Min 1.7 0.49 x VCC VREF-0.04 1.7 Typical 1.8 0.50 x VCC VREF Max 1.9 0.51 x VCC VREF+0.04 3.6 Unit V V V V Notes 3 1 2 Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC. OPERATING TEMPERATURE CONDITION Parameter Operating Case Temperature (commercial) Symbol TOPER Rating 0 to +85C Units C Notes 1, 2 NOTE: 1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2 2. At 0 to +85C, operation temperature range, all DRAM specification will be supported. April 2006 Rev. 2 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input High (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 WV3HG264M72EER-PD4 ADVANCED Max VCC + 0.300 VREF - 0.125 Unit V V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 1) Voltage DDR2-667 AC Input High (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 0) Voltage DDR2-667 Symbol VIH(AC) VIH(AC) VIL(AC) VIL(AC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Unit V V V V INPUT/OUTPUT CAPACITANCE TA=25C, f=100MHz Parameter Input capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#) Input capacitance (CKE0, CKE1), (ODT0, ODT1) Input capacitance (CS0# - CS1#) Input capacitance (CK, CK#) Input capacitance (DM0~DM8), (DQS0~DQS8) Input capacitance (DQ0~DQ63), (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (665) CIN5 (534, 403) COUT1 (665) COUT1 (534, 403) Min 11 11 11 10 9 9 9 9 Max 12 12 12 11 11 12 11 12 Unit pF pF pF pF pF pF pF pF April 2006 Rev. 2 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Includes DDR2 SDRAM components only VCC = +1.8V 0.1V Symbol ICC0* Proposed Conditions Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING WV3HG264M72EER-PD4 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS 806 TBD 665 1,337 534 1,292 403 1,292 Units mA ICC1* Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 TBD 1,472 1,427 1,427 mA ICC2P* TBD 644 644 644 mA ICC2Q** TBD 1,130 1,040 1,040 mA ICC2N** TBD 1,220 1,040 716 1,130 1,040 716 1,130 1,040 716 mA mA mA ICC3P** TBD TBD ICC3N** Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal TBD 1,490 1,400 1,400 mA ICC4W* TBD 1,832 1,652 1,562 mA ICC4R* TBD 1,877 1,697 1,562 mA ICC5B** TBD 3,200 3,020 3,020 mA ICC6** TBD 144 144 144 mA ICC7* Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. TBD 2,552 2,552 2,552 mA Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. *: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. April 2006 Rev. 2 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER CL = 6 CL = 5 CL = 4 CL = 3 SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS tIPW tIS tIH tCCD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD WV3HG264M72EER-PD4 ADVANCED AC TIMING PARAMETERS & SPECIFICATIONS 806 MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 665 MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 534 MAX 8,000 8,000 8,000 0.55 0.55 125 +450 MIN MAX MIN 403 MAX UNIT ps ps ps ps tCK tCK ps ps ps ps ps MIN 3,000 3,750 5,000 0.45 0.45 MIN(tCH,tCL) Clock cycle time Clock 3,750 5,000 0.45 0.45 MIN(tCH,tCL) 8,000 8,000 0.55 0.55 125 +500 tAC(MAX) 5,000 5,000 0.45 0.45 MIN(tCH,tCL) 8,000 8,000 0.55 0.55 125 +600 tAC(MAX) CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time -125 -450 -125 -500 -125 -600 tAC(MAX) tAC(MIN) 100 225 0.35 340 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 240 0.9 0.4 0 0.35 0.4 WL0.25 0.6 200 275 2 TBD TBD tAC(MAX) tAC(MIN) 100 225 0.35 tAC(MAX) tAC(MIN) 150 275 0.35 tAC(MAX) TBD TBD Data TBD TBD TBD TBD tCK 450 ps ps ns tCK tCK ps tCK tCK 350 ps tCK tCK ps tCK tCK tCK tCK ps ps tCK TBD TBD TBD TBD 400 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2 300 0.9 0.4 0 0.35 0.4 WL0.25 0.6 250 375 2 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD +400 +450 +500 Data Strobe TBD TBD 1.1 0.6 1.1 0.6 0.6 WL+ 0.25 0.6 WL+ 0.25 0.9 0.4 0 0.35 0.4 WL0.25 0.6 350 475 2 1.1 0.6 0.6 WL+ 0.25 TBD TBD TBD TBD TBD TBD TBD TBD * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page April 2006 Rev. 2 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to Active of Refresh to Refresh command interfal WV3HG264M72EER-PD4 ADVANCED AC TIMING PARAMETERS (cont'd) 806 SYMBOL tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF tAONPD TBD TBD 665 MAX TBD TBD TBD TBD TBD TBD TBD TBD 534 MAX MIN 60 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH 70,000 7.8 105 70,000 7.8 tRFC(MIN) +10 200 tIS 2 tAC(MAX) +1000 2.5 tAC(MAX) +600 2.5 x tCK+ tAC(MIN) +1000 2.5 x tCK+ tAC(MIN) +1000 2 tAC(MIN) 2.5 tAC(MIN) tAC(MIN) +2000 tAC(MIN) +2000 3 8 2 6-AL 2 3 2 tAC(MAX) +1000 2.5 tAC(MAX) +600 2.5 x tCK+ tAC(MIN) +1000 2.5 x tCK+ tAC(MIN) +1000 403 MAX MIN 55 7.5 15 37.5 40 7.5 15 tWR+tRP 10 15 tRP+tCK 2 tIS+tCK tIH 105 70,000 7.8 tRFC(MIN) +10 200 tIS 2 tAC(MIN) 2.5 tAC(MIN) tAC(MIN) +2000 tAC(MIN) +2000 3 8 2 6-AL 2 3 2 tAC(MAX) +1000 2.5 tAC(MAX) +600 2.5 x tCK+ tAC(MIN) +1000 2.5 x tCK+ tAC(MIN) +1000 MIN TBD TBD TBD TBD TBD TBD TBD TBD MIN 60 7.5 15 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK tIH 105 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns tCK ns ns s ns tCK ps tCK ps tCK ps ps Command and Address 37.5 70,000 37.5 70,000 37.5 70,000 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Self Refresh Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tRFC(MIN) +10 200 tIS 2 tAC(MIN) 2.5 tAC(MIN) tAC(MIN) +2000 tAC(MIN) +2000 TBD TBD TBD TBD ODT TBD TBD ODT turn-on (power-down mode) ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any nonREAD command. CKE minimum high/low time tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE TBD TBD TBD TBD TBD TBD ps tCK tCK tCK tCK tCK tCK 3 8 2 7-AL 2 3 Power-Down TBD TBD TBD TBD TBD TBD * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. April 2006 Rev. 2 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-PD4 ADVANCED ORDERING INFORMATION FOR PD4 Part Number WV3HG264M72EER806PD4xxG** WV3HG264M72EER665PD4xxG** WV3HG264M72EER534PD4xxG WV3HG264M72EER403PD4xxG Speed/Data Rate Frequency 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP ** Consult factory for availability NOTES: * RoHS compliant product (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR PD4 67.75 (2.667) 67.45 (2.656) 3.8 (0.150) MAX 4.10(0.161)(2X) 3.90(0.154) 1.80 (0.071) (2X) 30.15 (1.187) 29.85 (1.175) 20.00 (0.787) TYP 6.00 (0.236) 2.55 (0.100) 2.15 (0.085) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP PIN 1 0.45 (0.018) 0.60 (0.024) TYP TYP 2.504 (63.60) TYP PIN 199 BACK VIEW PIN 200 4.2 (0.165) TYP 47.40 (1.866) TYP 11.40 (0.449) TYP PIN 2 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) Tolerances: 0.13 (0.005) unless otherwise specified April 2006 Rev. 2 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-PD4 ADVANCED PART NUMBERING GUIDE WV 3 H G 2 64M 72 E E R xxx PD4 x x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V REGISTERED SPEED (Mb/s) PACKAGE 200 PIN SO-DIMM (P = JEDEC proposed pin-out) INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT April 2006 Rev. 2 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title WV3HG264M72EER-PD4 ADVANCED 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, SO-DIMM DRAM DIE OPTIONS: * SAMSUNG: C-Die, will move to E-Die Q2'06 * MICRON: U37Y: B-Die Revision History Rev # Rev 0 Rev 1 History Created 1.0 Update DC specification 1.1 Added "P" for JEDEC proposed pin-out 1.2 Added die rev info Release Date March 2006 April 2006 Status Concept Advanced Rev 2 2.1 Added VCCSPD voltage specification April 2006 Advanced April 2006 Rev. 2 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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